The XPS Universal Asynchronous Receiver Transmitter (UART) Lite Interface connects to the PLB (Processor Local Bus) and provides the controller interface for asynchronous serial data transfer.
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The UART Lite driver resides in the uartlite subdirectory. Details of the layer 1 high level driver can be found in the xuartlite.h header file. Details of the layer 0 low level driver can be found in the xuartlite_l.h header file. UART 16450/16550 The UART 16450/16550 driver resides in the uartns550 subdirectory. Details of the layer 1
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OPB_UARTLITE 0x4060_0000 0x4060_FFFF 64K bytes Serial Output OPB_GPIO 0x4002_0000 0x4002_FFFF 64K bytes LED output OPB_GPIO 0x4000_0000 0x4000_FFFF 64K bytes Push Buttons PLB_EMC 0x0000_0000 0x0000_FFFF 1M bytes External Memory Controller Table 1: Tutorial Design Memory Map 2 www.xilinx.com EDK 7.1 PowerPC Tutorial in Virtex-4
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Description opb_usblite - opb_uartlite replacement for Xilinx Microblaze processor written in VHDL and Verilog. The opb_usblite is compatible with the USB CDC profile and works with microsoft usbser virtual comport driver (VCD).
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- Device Drivers -> Character devices -> Serial Drivers -> Xilinx uartlite serial port support (using uartlite core in PL) Disabled drivers. - Device Drivers -> GPIO Support -> Memory mapped GPIO drivers -> Xilinx GPIO support (using my original gpio driver) Auto-mount Description. Modify fstab as,
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Xilinx Device Drivers Driver Summary Copyright Main Page Data Structures File List Data Fields Globals. The UART Lite driver resides in the uartlite subdirectory.